cache issues

As far as I know, the D-cache in Nios II 1.0.1 works fine (there was a bug in Nios II 1.0).

I did find a bug in the Nios II/f core regarding interrupts and writes to the ienable register that is fixed in Nios II 1.1.

This bug looks like a spurious interrupt. I'm not familiar enough with the uClinux code to know what it does

in this case but it could be your problem.

I'd recommend that you try a simple experiment to see if your problem is

with the D-cache or just the Nios II/f in general. Just edit your system.ptf file (make sure SOPC Builder isn't running)

and change always_bypass_dcache from "0" to "1". Now regenerate in SOPC Builder, recompile your software,

and try again. If you still have a problem, it isn't the D-cache because you just disabled it.

As for how to initialize the caches, I would hope the that the uClinux startup code at the reset address

takes care of this for you. You should see it executing initi instructions in a loop to clear out the I-cache

and initd instructions in a loop to clear out the D-cache.

BTW, when you say the CPU is dead, what exactly do you mean by dead? If you have the OCI debug built-in,

are you able to single-step or break the CPU? You could enable Signaltap II and look at signals to see what

the CPU is doing while it is dead. I'd recommend looking at A_pc, A_valid, A_iw, and A_stall. The A_pc is the A-stage

word-aligned instruction address (multiply by four to get a byte address). The A_valid tells you if there is an

instruction in the A-stage. The A_iw tells you which instruction is present (32-bit instruction). The A_stall tells you

if the A-stage (and all other stages as well) are stalled.