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Altera_Forum's avatar
Altera_Forum
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14 years ago

Burst transfer from memory to Nios II

Hello, I have a hard time understanding how the Nios II handles memory accesses. In our Nios II design we want to use burst transfers to transfer data from SRAM into the caches of the proc...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Or give the nios 'tightly coupled' access and let the SGMA access the other as an Avalon slave.

If you are using on-chip memory for code/data the performance is better if you use tightly coupled memories. It may well mean that you don't need the instruction or data caches (except you'll need the i-cache to use the JTAG debug and most of the boot options).

You do want to make sure that the code put into tightly coupled instruction memory is pure (contains no data) - to avoid slow Avalon cycles to it. This probably required you use a non-standard linker script and may be impossible if you are trying to use the default EPCS loader. Also the gcc4 built by Altera puts jump tables (for switch statemants) into the code segment - you'd need to use the gcc3 build (or rebuild the compiler).

I also got worse code from gcc4!