Building a SDRAM controller

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originally posted by zaphod@Oct 18 2006, 12:15 PM

hi.....im quite new to the altera de2 board, and i have a very fundamental question. lets say i wanted to build hardware that does y = (a+http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/cool.gif *c where a is my input and b and c are prestored values in the sdram. the final output y also goes to the sdram.

a)how do i build a sdram controller that i can integrate with my verilog code (for the above function)? all the tutorials keep talking about using c or assembly to do the function which i dont want to do.

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I don&#39;t think you want to build your own SDRAM controller. You want to write your own Avalon component (presumably a master) that does this. Or, you could just use C2H and let it do the job for you.

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originally posted by zaphod@Oct 18 2006, 12:15 PM

http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/cool.gif how do i use the burst modes in these?

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If you&#39;re using the Altera-provided SDRAM controller, I don&#39;t think enabling burst will help you. The Microtronix SDRAM controller does support bursting....so you might want to have a look at that. For a sample of an Avalon master (that supports bursting), you could take a look at the provided Avalon DMA controller.

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originally posted by zaphod@Oct 18 2006, 12:15 PM

sorry if this seems trivial and thanks for the help in advance. http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/smile.gif

-zaphod

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Best Regards,

- slacker

Ok so lets say I have hardware that does this -> Y=5*a . It takes data from 1 memory location , feeds it to &#39;a&#39; and then stores the result &#39;Y&#39; in the same memory location. The module has an address generator which increments the address every clock cycle. So now I have 1 &#39;clock&#39; input, 1 &#39;address&#39; output, 1 &#39;data&#39; inout.

Now in my head, I have 3 parts to the system - my hardware, the NIOS system, and the SDRAM. The SDRAM is connected to the SDRAM controller (built as part of the NIOS system). My hardware is connected to the NIOS system as well. I have no use for the processor since im not going to run any C code on it. All it does is provide a master device for my SDRAM controller. (The only reason im using the NIOS is to get the SDRAM controller)

How do I get NIOS system to redirect the address I generate to the SDRAM and get the data back and forth between my hardware and the SDRAM?

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originally posted by zaphod@Oct 18 2006, 11:15 PM

ok so lets say i have hardware that does this -> y=5*a . it takes data from 1 memory location , feeds it to &#39;a&#39; and then stores the result &#39;y&#39; in the same memory location. the module has an address generator which increments the address every clock cycle. so now i have 1 &#39;clock&#39; input, 1 &#39;address&#39; output, 1 &#39;data&#39; inout.

now in my head, i have 3 parts to the system - my hardware, the nios system, and the sdram. the sdram is connected to the sdram controller (built as part of the nios system). my hardware is connected to the nios system as well. i have no use for the processor since im not going to run any c code on it. all it does is provide a master device for my sdram controller. (the only reason im using the nios is to get the sdram controller)

how do i get nios system to redirect the address i generate to the sdram and get the data back and forth between my hardware and the sdram?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18784)

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SDRAM controller core appears on the Avalon bus gives software abstracts of your whole SOPC system, hardwares are transparent. If you do care too much about timing and dedicated memory access, you might have to build your own huge physical memory control scheme.

Simply saying connecting SDRAM to Nios using SDRAM controller doesn&#39;t give any hardware access to your HDL. You will have to use Nios HAL to access component like the drivers developed for your custom design peripheral.

zaphod, from reading your posts I understand you don&#39;t want to use the NIOS processor, but you just want to access some SDRAM chips from your custom FPGA logic.

If this is true, then using the term "NIOS system" in your post is incorrect - you don&#39;t have any NIOS processor there. You want to call it "SOPC Builder module" or "Avalon switch fabric module" for example, because it&#39;s the logic automatically generated by SOPC Builder which contains the point-to-point Avalon bus logic between your (custom) master and peripherals (SDRAM controller in this case).

Now to answer your question: you want to perform a read-modify-write operation from your Verilog custom logic into the SDRAM.

You need to write your custom logic to be an Avalon master (refer to Altera docs on how to do this). Your custom master will have to handle the address generation and the wait states/latency of a generic Avalon slave (Altera docs tell you how to do this) - no need to delve into the intricacies of an SDRAM controller.

You can use Altera&#39;s SDRAM controller provided with Quartus/NIOS tools. Just create a SOPC Builder module and add these 2 components: Altera SDRAM controller, and your custom Avalon master. Make sure you hardcode the memory base address correctly in your master, or make it configurable. Generate the SOPC system and DONE!

Regarding the burst mode, Altera&#39;s SDRAM controller is not capable of burst mode access, you will have to switch to DDR, or buy an SDRAM controller IP from another company, or write your own http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

Good luck!