Building a SDRAM controller

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originally posted by zaphod@Oct 18 2006, 11:15 PM

ok so lets say i have hardware that does this -> y=5*a . it takes data from 1 memory location , feeds it to 'a' and then stores the result 'y' in the same memory location. the module has an address generator which increments the address every clock cycle. so now i have 1 'clock' input, 1 'address' output, 1 'data' inout.

now in my head, i have 3 parts to the system - my hardware, the nios system, and the sdram. the sdram is connected to the sdram controller (built as part of the nios system). my hardware is connected to the nios system as well. i have no use for the processor since im not going to run any c code on it. all it does is provide a master device for my sdram controller. (the only reason im using the nios is to get the sdram controller)

how do i get nios system to redirect the address i generate to the sdram and get the data back and forth between my hardware and the sdram?

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SDRAM controller core appears on the Avalon bus gives software abstracts of your whole SOPC system, hardwares are transparent. If you do care too much about timing and dedicated memory access, you might have to build your own huge physical memory control scheme.

Simply saying connecting SDRAM to Nios using SDRAM controller doesn&#39;t give any hardware access to your HDL. You will have to use Nios HAL to access component like the drivers developed for your custom design peripheral.