jman,
That's what should happen. The epcs_controller has a small onchip memory where a bootloader resides. This bootloader is responsible for detecting the end of the SOF in the EPCS device and loading code from that point on. If you set the reset address, in SOPC Builder, to point at the epcs_controller, and point the linker towards SRAM, you should be OK. You'd then want to use the Nios II Flash Programmer to program your EPCS with both your hardware and software images. It will create .flash files, for each, and write them into the EPCS device. As as aside, it's probably worth your time to review the Nios II Flash Programmer's guide as there are some really useful commands for debugging flash issues.
Depending on the size of your software, you might want to enable SOF compression for your hardware image.
If you want to use the EPCS device for something more, you could look at installing uCLinux, and the appropriate driver....or you could use the EPCS virtual memory component (
http://forum.niosforum.com/forum/index.php?showtopic=25).
Cheers,
- slacker