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Altera_Forum's avatar
Altera_Forum
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15 years ago

Basic questions about FIFO, IRQs & DMA

Hello, i used a fifo from the megawizard library and introduced it into the SOPC system (just the DATA and the HALF_FULL signals the others signals are exported to outside the sopc system).

How can i write DATA to the fifo? I see there are wrreq and rdreq signals.(both outside my sopc system).

How can i read the fifo from the DMA?

And the last question is: I set the HALF_FULL signal as an IRQ, how can i program it in C using NIOS?

Thanks a lot.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    My system looks like this (attached image)

    And here is my code 

    #include <stdio.h># include <stdlib.h># include <stddef.h># include <string.h>
# include <system.h># include <io.h>
# include <alt_types.h># include "sys/alt_dma.h"# include "sys/alt_cache.h"# include "sys/alt_alarm.h"# include "alt_types.h"
static volatile int txrx_done = 0;
int i;
//callback function when DMA transfer done
static void txrxDone(void * handle, void * data)
{
    txrx_done = 1;
}
void initMEM(int base_addr,int len)
{
    for ( i=0;i<len;i++)
    {
        IOWR_8DIRECT(base_addr,10,i);
    }
}
int main()
{
    printf("testing ssram & sdram : dma operation\n");
    alt_16 buffer;
    //memset((void *)SSRAM_0_BASE,0x7a,0x10);//this write base on byte
     initMEM(ONCHIP_MEMORY2_0_BASE,0x10);
   // memset((void *)(SDRAM_0_BASE),0x33,0x10);
    printf("content of ssram_0:before DMA operation\n");
    for ( i=0;i<0x10;i++)
    {
        printf("%d: %x\n",i,IORD_8DIRECT(DMA_0_READ_MASTER_MY_FIFO_BASE,i));
    }
    printf("content of sdram_1:before DMA operation\n");
    for ( i=0;i<0x10;i++)
    {
        printf("%d: %x\n",i,IORD_8DIRECT(ONCHIP_MEMORY2_0_BASE,i));
    }
    int rc;    //request
    alt_dma_txchan txchan;
    alt_dma_rxchan rxchan;
    void* tx_data = (void*)DMA_0_READ_MASTER_MY_FIFO_BASE; /* pointer to data to send */
    void* rx_buffer = (void*)(ONCHIP_MEMORY2_0_BASE); /* pointer to rx buffer */
    /* Create the transmit channel */
    if ((txchan = alt_dma_txchan_open("/dev/dma_0")) == NULL)
    {
        printf ("Failed to open transmit channel\n");
        exit (1);
    }
    /* Create the receive channel */
    if ((rxchan = alt_dma_rxchan_open("/dev/dma_0")) == NULL)
    {
        printf ("Failed to open receive channel\n");
        exit (1);
    }
    /* Post the transmit request */
    if ((rc = alt_dma_txchan_send (txchan,
            tx_data,
            0x10,
            NULL,
            NULL)) < 0)
    {
        printf ("Failed to post transmit request, reason = %i\n", rc);
        //exit (1);
    }
    /* Post the receive request */
    if ((rc = alt_dma_rxchan_prepare (rxchan,
            rx_buffer,
            0x10,
            txrxDone,
            NULL)) < 0)
    {
        printf ("Failed to post read request, reason = %i\n", rc);
        //exit (1);
    }
    /* wait for transfer to complete */
    while (!txrx_done);
    printf ("Transfer successful!\n");
    printf("content of ssram_0:after DMA operation\n");
    for ( i=0;i<0x10;i++)
    {
        printf("%d: %x\n",i,IORD_8DIRECT(DMA_0_READ_MASTER_MY_FIFO_BASE,i));
    }
    printf("content of sdram_1:after DMA operation\n");
    for ( i=0;i<0x10;i++)
    {
        printf("%d: %x\n",i,IORD_8DIRECT(ONCHIP_MEMORY2_0_BASE,i));
    }
    return 0;
}