Honored Contributor
Honored Contributortoday we noticed that when our writemaster writes to external sram and software uses a ldwio command on a nios2 fast cpu core to read the data, the cpu reads old memory content and not that what is realy there.
disabling the datacache solved these wrong reads. again we use ldwio (for 32bit) that should read regardless what is inside the datacache, but here with this fast core we read with ldwio the old content. disabling the datacache inside sopc and regenerate solved that for now. has anybody else here implemented a sopc modul with 3 interfaces (1 slave and 2 master) running on a fast core with datacache ? we nearly get crazy about that what is going on here. the external memory delivers the correct data that is written by the master but the software receives with a ldwio the contect before the avalon master had written .... maybe the avalon switch fabric has a problem but where can we look at ? Regards. Michael Schmitt (still hoping someone can point to the source of this)
