Honored ContributorIt is possible to create a component (ex. UART) with avalon MM slave interface with 8 bit data width and use it with Nios II with 32 bit bus?
I tried and compile fine but Nios II don't start on real fpga.. Thank you
Honored ContributorByte-enables are usually used during writes, asserting all high for writing words, partly for halfword and byte.
Nios does toggle the byteenable for reads but it stills reads 32-bit word. The byteenable can be used by the slave for byte-lane enabling depending on the slave use case. For example, the Onchip-Memory uses byte-enable for word/partial write but always returns 32-bit data for read. Qsys interconnect should help to perform data width adaptation to match the master-slave interfaces.
