Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Avalon - Tri-state bridge

I read document "Avalon Bus Specification - Refernce Manual" and I learned how Avalon bus is so flexible in the bus width - I know I can connect 8-bit or 16-bit slave to 32-bit master with no problems...

So I went off to do it in real life and my problems started. I have a custom "daughter" card which stick into my custom Cyclone board (not any of Altera evaluation boards) and I have a regular Flash, RTC clock with battery and three SRAM memory chips on this card. The card interfaces with 24-bit tri-state address bus and 16-bit tri-state data bus.

How to configure Avalon tri-state bridge to get the correct bus width? I see only "registered/not registered" option. How to deal with 24-bit address and 16-bit data bus? Where do I pick "dynamic bus sizing" scheme for my Flash and SRAM chips and "native aligment" for my RTC chip I read about in the book?? I need to split them two probably into two different "components" having own addressing aligment for each, but how to do it?? Where can I read about using SOPC builder for this purpose?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    21 years ago

    Pszemol,

    Kenland is right. You need to create an interface to user logic for each peripheral/memory bank you want to address on your card. When you go through the wizard, selecting the data bus type to "inout" (bi-directional) will tell SOPC Builder that this is a tri-state bus. When you're done with the wizard, you hook up the new slave to a tri-state bridge.

    You should note that certain signals can be shared... so if you have (for example), a tri-state bus with shared read/write/address/data lines for all peripherals but unique chip selects, you'll have to tell the wizard this as you create each interface. This will affect he pins that pop out on the top-level of the SOPC Builder design.

    Finally, when you choose "Avalon Register Slave" in the wizard, you're specifying the native addressing mode. When you specify "Avalon Memory Slave", you're specifying dynamic alignment. This is detailed in the avalon bus spec.