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PHJ's avatar
PHJ
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7 years ago

Arria 10 HPS I/O Pin Multiplexing configuration

​The A10 HPS technical reference manual has the following note for each of the pinmux configuration registers (e.g. pinmux_uart0_usefpga) : "NOTE: These registers should not be modified after IO con...
a_x_h_75's avatar
a_x_h_75
Icon for Contributor rankContributor
7 years ago

This refers to the fact that these multiplexing options are determined by the FPGA's programming bitstream (the result of compiling your design through Quartus) and can't be modified by the function of the fabric - i.e. your FPGA code. The function of these pins is fixed for a given FPGA configuration image (bitstream).

Cheers,

Alex