Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Arria 10 fPLL lock problem

Hi all, I have a design that uses the fPLL in Core mode (transceivers are not used) to generate some clocks, the problem is that it never finishes the calibration, pll_cal_busy stays high; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

Apologies for the late response.

Calibration is not required.

I have checked with Reference clock frequency of 40MHz and output clock frequency of 24MHz.

Also checked with Reference clock frequency of 150MHz and output clock frequency of 50MHz

The pll_cal_busy signal goes low after 580 ns and pll_locked is asserted.

Also, check below link may be it helps.

https://www.alteraforum.com/forum/showthread.php?t=55008

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)