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Altera_Forum's avatar
Altera_Forum
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8 years ago

Arria 10 fPLL lock problem

Hi all, I have a design that uses the fPLL in Core mode (transceivers are not used) to generate some clocks, the problem is that it never finishes the calibration, pll_cal_busy stays high; ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hi,

Thank you for the reply.

Adding a reset didn't solve the problem; I disabled the fPLL reset-calibration link with:

set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_DISABLE_RESET_CONNECTED_TO_CAL_BUSY=1"

and now the PLL locks. pll_cal_busy was keeping the PLL in reset.

pll_cal_busy is still active so the question remains:

Do I need the calibration for the fPLL to work correctly in "Direct" mode?

Best regards,

Jakab