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Altera_Forum's avatar
Altera_Forum
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8 years ago

Arria 10 fPLL lock problem

Hi all, I have a design that uses the fPLL in Core mode (transceivers are not used) to generate some clocks, the problem is that it never finishes the calibration, pll_cal_busy stays high; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

Maybe because of reset.

Have you reset the PLL?Use pll_powerdown to reset.

If you don't want the pll_cal_busy then use CMU PLL.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)