Forum Discussion
gcohe5
New Contributor
6 years agohi,
no, i'm doing it the other way now (copying EPCQ to RAM).
...but i do have some questions regarding the new method:
- I've found that in order for the SW to upload after power up the nios reset needs to be delayed for some cycles (no sure exactly how many), do you know why this is?
- I'm trying to configure the fpga with EPCQ (as described above) and booting linux with an sd card (when creating the boot file in bsp-editor I checked external_fpga_config box) when using the delay (== counter on top level holding the reset for the nios qsys enabled) the boot gets stuck and the linux does not load , do you know why this may be? can it be connected to the delay i'm implementing?
thanks!