ARM DS-5 device_browser.py failed

This issue has not been resolved in the current version of Quartus. I am using version 15.0

and i got the following error message when trying to debug the example project called:

Altera-SoCFPGA-HelloWorld-Baremetal-GNU

the script file ( device_browser.py ) failed during execution:

error: failed to load client library libjtag_client.so.

please ensure that the environment variable quartus_rootdir is set to the path to the altera quartus tools installation.

I did the same thing that other guy did, in that i echoed the variable and confirmed that it was

indeed set properly and it is.

Another thing is that my arm compiler doesn't seem to work due to some licensing error. When I

try to build any of the ARMCC examples (i know that most of them are for cyclone V, not Arria)

I get this message:

7:16:31 **** build of configuration debug for project altera-socfpga-helloworld-baremetal-armcc ****

make all

building file: ../hello.c

invoking: arm c compiler

armcc --cpu=cortex-a9.no_neon.no_vfp -o0 -g --md --depend_format=unix_escaped -c -o "hello.o" "../hello.c"

product: ds-5 altera edition 5.20.2 [5202025]

error: c9555e: license checkout for feature altera_compiler5 with version 5.0201411 has been denied by flex back-end. error code: -5

component: arm compiler 5.05 update 1 (build 106)

no such feature exists.

tool: armcc [4d0efa]

feature: altera_compiler5

license path: /home/zyvexlabs/downloads/altera/c03fd56ed3f2_1435861502441.dat:/opt/arm/licenses/license.dat:

flexnet licensing error:-5,357

for further information, refer to the flexnet licensing documentation,

available at "www.flexerasoftware.com (http://www.flexerasoftware.com)".

make: *** [hello.o] error 1

I am using the Arria V Soc Development Board (5ASTFD5K3F4013N). My host/dev PC is an

intel NUC i5 running Ubuntu 14.04. I have the full quartus licence.

My goal is to create a working architecture for the Arria V SoC Dev Kit which allows us to:

1.) Dedicate one core of the ARM to doing the scan loop and nothing else.

2.) Also the ARM core dedicated to the scan loop cannot be interfered with

by kernel level interrupts related to other processes being run on the other

core by a linux smp.

3.) That is to say that the scan loop core should run bare metal or with an

RTOS (which only support use of one core) making the system as a whole

an AMP system.

4.) Furthermore one the other portions of the AMP system whether it be the FPGA

or the other ARM core must be able to run a working TCP stack and have access

to enough memory in order to facilitate the large size of the buffers that we are moving.

5.) Also one portion of the FPGA must be dedicated to receiving and transmitting

data from and to the ADCs and DACs.

6.) All of these portions of the system must pass data to and from the bare metal

scan loop directly (the adc/dac vals and the cmd/stat buffers). This will most

likely be achieved through very carefully implemented shared memory access.

7.) The preferred implementation would be:

ARM core 1: Bare metal Scan loop ----->[ARM core 1 Memory | shared |]

ARM core 2: Linux TCP stack----------->[ARM core 2 Memory | memory |]

FPGA: ADC/DAC vals-------------------->[FPGA Memory______ | access |]

8.) However if# 7 cannot be achieved any implementation that satisfies# 1 -# 6

is acceptable. For example:

ARM core 1: Bare metal Scan loop ----->[ARM core 1 Memory | shared |]

FPGA: Nios2 Linux TCP stack----------->[FPGA Memory______ | memory |]

FPGA: ADC/DAC vals-------------------->[FPGA Memory______ | access |]

There are many more options especially when considering the use of RTOSes like

FreeRTOS or uCosII etc...

As of yet I have been completely unsuccessful in achieving this architecture.

Someone please help me....