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Altera_Forum
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7 years ago

Altera Cyclone V: UDP data transfer without packet loss

Dear all, I am a newbie in Altera Cyclone V SOC. We are conducting a feasibility study on our Altera Cyclone V SOC. We are having some streaming data receiving at FPGA at 300 Megabits p...
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Altera_Forum
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7 years ago

Yes putting the system timer to 1ms instead of 10ms will cause a bit more overhead, but also a better granularity on how the processor power is distributed between the tasks. On an non-RT operating system it could make a difference, it can be worth it to try. I don't think the overhead is that high for a >600MHz CPU.

As for you other question I'm sorry but as I said I'm not familiar with embedded Linux. If you don't find any answer here maybe you could try a more generic ARM Linux forum.

We are using eCosPro ourselves but I think some people have also been successful with FreeRTOS on the SoC platform.