Altera Avalon Uart performance problem

Thanks for the suggestion. Now that you've mentioned this, it seems quite obvious that this would alleviate the problem. I've already implemented this on the receive side, so that a threshod is reached before generating the interrupt.

I've verified that the receive_chars() routine will indeed read in all characters within the fifo on a single call.

Will the transmit_chars() routine perform the same operation? It should be able to write characters to the transmit buffer until it is full (or nearly full).

In looking at it, it appears that it will only send 1 character per interrupt. Am I right?

Do you have some suggested ways of handling this?

I can think of a possible implementation.

Perform a do/while loop similar to the one in receive_chars() that will write chars to the tx fifo until it is full.

If necessary, the uart w/ fifo support does provide new registers that allow software to see how many characters are in the fifo.

This value could be used so the transmit_chars() routine knows when to stop writing data to the uart.

If this fifo count info is important, I can add it to the serial driver. However, I do have some questions about how to add it.

The registers below exist at offsets 6 and 7 of the uart. I'm not sure how to adjust the structure to make these readable from within the driver.

np_uartrxfifoused address 6

np_uarttxfifoused address 7

Am I on the right track? Does the transmit_chars() routine need to be modified?

Thank you very much for you help.

P.S. If I get all of this working, I'll add a timer-based irq event into the uart so that if there are any characters in the rx buffer, an irq will be generated every X ms. This will ensure no characters are left sitting in the receive fifo because the threshold hasn't been reached yet.