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Altera_Forum's avatar
Altera_Forum
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21 years ago

Adresses of user logic

Hello,

I've added a user logic block with the NIOS2 core via tha Avalon bus. The Base Adress is 0x00940000 - 0x0097FFFF. There are two ports: 16 bit input and 16 bit output. How do I interface them by software? What are the adresses of the ports?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    21 years ago

    > What are the adresses of the ports?

    There's no mmu involved. The addresses will be the same: 0x00940000 - 0x0097FFFF.

    --Scott
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    21 years ago

    PS:

    for II/s and II/f cores, you may want to use bit-31 cache bypass, i.e. :

    0x00940000 - 0x0097FFFF ==> 0x80940000 - 0x8097FFFF

    Also, if you plan on using ioremap_nocache() in your driver, you might

    want to check it's implementation. In the kernel version I'm using,

    ioremap_nocache() simply returns the physical pointer that's passed

    in -- which really isn't what you want (or expect) for II/s & II/f. I'm not

    sure if this was updated in the latest version.

    I patched ioremap_nocache to return the pointer with bit-31 set after

    invalidating the dcache region.

    --Scott