Address Exception

Hi

We are using a SRAM that has a 16-bit wide data bus and /BLE and /BHE signals for byte-write.

Writing bytes to addresses 0 to 7 works, with BLE and BHE behaving as expected, although A0 is always at logic 0 (so presumably we must connect A1..A18 to the SRAM).

Writing words to addresses 0 to 3 is fine when the addresses are even. When the addresses are odd, though, writing $55AA to the SRAM causes 2 write cycles to consecutive addresses, BUT $55AA is presented on the data bus throughout. So writing $55AA to address 1 causes the bytes $AA,$55,$AA,$55 to appear from addresses 0 to 3, which is clearly wrong. No BLE or BHE activity appears.

This reminds me very much of my 68000 days. Is there an address exception? If so this kind of "misbehaviour" could be OK if an exception is raised.

The PTF file contents are below (note we're using the "dynamic bus sizing[memory]" option):

##  This class.ptf file built by Component Editor#  2005.06.23.15:36:32# #  DO NOT MODIFY THIS FILE#  If you hand-modify this file you will likely#  interfere with Component Editor's ability to#  read and edit it. And then Component Editor#  will overwrite your changes anyway. So, for#  the very best results, just relax and#  DO NOT MODIFY THIS FILE# 
CLASS is61lv256
{
  ASSOCIATED_FILES 
  {
    Add_Program = "the_wizard_ui";
    Edit_Program = "the_wizard_ui";
    Generator_Program = "cb_generator.pl";
  }
  MODULE_DEFAULTS 
  {
    class = "is61lv256";
    class_version = "2.0";
    SYSTEM_BUILDER_INFO 
    {
      Instantiate_In_System_Module = "0";
      Is_Enabled = "1";
      Date_Modified = "--unknown--";
      Top_Level_Ports_Are_Enumerated = "1";
    }
    WIZARD_SCRIPT_ARGUMENTS 
    {
    }
    SIMULATION 
    {
      DISPLAY 
      {
      }
    }
    COMPONENT_BUILDER 
    {
      GLS_SETTINGS 
      {
      }
    }
    PORT_WIRING 
    {
    }
    SLAVE avalonS
    {
      SYSTEM_BUILDER_INFO 
      {
        Bus_Type = "avalon_tristate";
        Address_Width = "18";
        Address_Alignment = "dynamic";
        Data_Width = "16";
        Has_Base_Address = "1";
        Has_IRQ = "0";
        Setup_Time = "10ns";
        Hold_Time = "10ns";
        Read_Wait_States = "20ns";
        Write_Wait_States = "20ns";
        Read_Latency = "0";
        Maximum_Pending_Read_Transactions = "0";
        Is_Printable_Device = "0";
        Is_Memory_Device = "1";
        Is_Readable = "1";
        Is_Writable = "1";
        Minimum_Uninterrupted_Run_Length = "1";
      }
      COMPONENT_BUILDER 
      {
        ATS_SETTINGS 
        {
          Setup_Value = "10";
          Read_Wait_Value = "20";
          Write_Wait_Value = "20";
          Hold_Value = "10";
          Timing_Units = "ns";
          Read_Latency_Value = "0";
          Max_Pending_Read_Transactions_Value = "1";
          Address_Alignment = "dynamic";
          Is_Printable_Device = "0";
          interface_name = "Avalon Tristate Slave";
          Minimum_Arbitration_Shares = "1";
          external_wait = "0";
          Is_Memory_Device = "1";
        }
      }
      PORT_WIRING 
      {
        PORT Adds
        {
          width = "18";
          width_expression = "";
          direction = "input";
          type = "address";
          is_shared = "1";
        }
        PORT Data
        {
          width = "16";
          width_expression = "";
          direction = "inout";
          type = "data";
          is_shared = "1";
        }
        PORT WE_N
        {
          width = "1";
          width_expression = "";
          direction = "input";
          type = "write_n";
          is_shared = "0";
        }
        PORT OE_N
        {
          width = "1";
          width_expression = "";
          direction = "input";
          type = "read_n";
          is_shared = "0";
        }
        PORT SRAM_CE_N
        {
          width = "1";
          width_expression = "";
          direction = "input";
          type = "chipselect_n";
          is_shared = "0";
        }
        PORT avalon_clk
        {
          width = "1";
          width_expression = "";
          direction = "input";
          type = "clk";
          is_shared = "0";
        }
        PORT BE
        {
          width = "2";
          width_expression = "";
          direction = "input";
          type = "byteenable_n";
          is_shared = "1";
        }
      }
    }
  }
  USER_INTERFACE 
  {
    USER_LABELS 
    {
      name = "IS61LV256";
      technology = "User Logic";
    }
    WIZARD_UI the_wizard_ui
    {
      title = "IS61LV256 - {{ $MOD }}";
      CONTEXT 
      {
        H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
        M = "";
        SBI_ = "SYSTEM_BUILDER_INFO";
        SBI_avalonS = "SLAVE avalonS/SYSTEM_BUILDER_INFO";
      }
      PAGES main
      {
        PAGE 1
        {
          align = "left";
          title = "IS61LV256 2.0 Settings";
          layout = "vertical";
          TEXT 
          {
            title = "Built on: 2005.06.23.15:36:32";
          }
          TEXT 
          {
            title = "Class name: is61lv256";
          }
          TEXT 
          {
            title = "Class version: 2.0";
          }
          TEXT 
          {
            title = "Component name: IS61LV256";
          }
          TEXT 
          {
            title = "Component Group: User Logic";
          }
        }
      }
    }
  }
  DEFAULT_GENERATOR 
  {
    top_module_name = "";
    black_box = "1";
    vhdl_synthesis_files = "";
    verilog_synthesis_files = "";
    black_box_files = "";
  }
  COMPONENT_BUILDER 
  {
    CACHED_HDL_INFO 
    {
     #  cached hdl info, emitted by cbGuinevereApp.CBFrameRealtime.getDocumentCachedHDLInfoSection:123
     #  used only by Component Builder
    }
    HDL_PARAMETERS 
    {
     #  generated by cbDocument.CBDocument.getParameterContainer:385
     #  used only by Component Editor
    }
    SW_FILES 
    {
    }
    built_on = "2005.06.23.15:36:32";
  }
  CB_GENERATOR 
  {
    HDL_FILES 
    {
    }
    top_module_name = "";
    emit_system_h = "0";
  }
  SOPC_Builder_Version = "5.00";
}