Accelerating a C Function with User Logic

Just think about how the cpu pipeline works.

AFAICT the clock sequence is basically:

1) Read instruction word.

2) Use A and B fields to read two register values from dual ported M9K.

3) Combinatorial ALU results feed in a big mux, result selected by the opcode.

4) Writeback any result to specified register.

(there is probably an additional clock in there somewhere - mainly for avalon accesses)

This means that an instruction only has the instruction word and the values of the A and B registers available, and can write to a single register.

For combinatorial ALU operations there is a store-to-load forwarder so that the result from one instruction is available to the next without going through the register file.

For other instructions (eg memory read) the value has to go through the register file, so the pipeline stalls (re-executes clock 2) until the needed data will be valid.

For custom instructions this stall is documented as being controlled by the readra/b bits.