Accelerating a C Function with User Logic

Maybe you can break the function up into several pieces - so that the nios cpu can execute the second 'user function' between the blocks of VHDL.

If the FP operations dominate, trying to do them from VHDL may just eat up fpga real estate - without really making things significantly faster.

The other question is 'how much too slow', you may be able to gain enough by ensuring there are no unnecessary memory accesses, cycle stalls (eg late result after memory read or custom instructions), cache misses (use tightly coupled memory), or incorrectly predicted branches (disable dynamic branch prediction and ensure the static prediction is correct).