About the Speed of SPI IP in Qsys in continually transmission

That GAP of time is taking about 15 clock cycle(300/20). I think some delay should be expected when you are using IP API in NIOS core and not directly going through custom RTL. When sending command or reading back its status register, it would take some clock cycles in the process,esp in the Qsys interconnect (between master and slave). Also, by looking at the description https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf, pg37 SPI core, it is designed to transfer single data word at a time and not support for continuous writing data to SPI slave.