about the CFI (FLASH) ?

In the nios_flash_programmer datasheef describe:

"If there are other non-flash devices on the same external tri-state

bus, you must add output pins for their output enable (OE), read

enable, or other such pins. The pins must be connected to either

GND or VCC, depending on the polarity of the external device pin

to disable the output from the other devices. Otherwise, there

will likely be tri-state bus contention, and damage to the devices

or the FPGA¡¯s can occur. "

so ,i think ,it is main: the flash_control_pin (as CS,OE,RE..) can not share tri_state bus with other non_flash devices_control_pin, like sram?? if like this ,now ,how to control the sram ???

thanks,for you help!!!