Honored Contributor
Honored ContributorNo it's not necessary but I highly recommend having one. When you are sampling from the ADC you don't want to run into cases where the SGDMA back-pressuring causes you to loose samples. With a FIFO you can help prevent these cases since the FIFO will fill up as apposed to samples being lost. The easiest way is to use the DCFIFO megafunction which you clock at the same rate as the ADC on the input side and use the SGDMA clock frequency on the output side of the FIFO. You drive the output into the SGDMA as a Avalon-ST source interface with the valid signal connected to 'FIFO not empty' and drive the FIFO read acknowledge with 'FIFO not empty & source ready'.
You can use the dual clock FIFO component in Qsys to do this and just export the input side out of the system and hardcode the valid signal into it to constantly write samples into it as well.
