A question on Addressing of peripherals in Qsys

You need to read the documentation for the PIO core. First the PIO core uses 32 bit registers, independently of how many actual PIO bits you have. Then you have several 32-bit registers. The registers at offset 0 is of course to read or write the PIO bits, but then you have others related to edge detection or interrupt generation.

When you say waste of resources, if you mean waste of logic elements in the FPGA, if you disabled all the extra features in the PIO that you don't need then the registers won't be synthesized and you won't waste logic. If you are talking about address space then yes you are wasting a bit but if you are really that tight in address space usage then you should probably design your own PIO that would just use one register. But the PIO core is using only 16 bytes out of a 4294967296 bytes address space. It's really not that much.