4-NIOS design, only processor 0 fails to boot from flash at power-on

To be honest, I don't know how *I'm* sequencing the boot (since I'm not)? The altera tools/code do an awesome job of making it easy to get things up and running.

The boot loader is Altera's out-of-the-box boot copier that's inserted with elf2flash utility. If the altera-boot copier does nothing for sequencing, then I'm not sequencing the boot.

I do know my "local asic guy" put in a flash arbitration module that allows multi-processor access to the flash. We are using a CFI flash part. We're not sharing memory between the 4 processors. The NIOS's are "stamped" out completely independently.

There's obviously a chance there's something broken in the flash arbitration, perhaps a race condition that only hits at power on, versus reset. It's still pretty interesting that only nios[0] fails at power on, but all 4 nios boot after a push of the reset button. One other point, to save time on the FPGA builds, I can build only a single "slice" of our design. In that case, there is only processor (nios[0]), and it still fails to boot at power-on, but succeeds after the reset button.

Thanks for the questions, I'll dig deeper on my side.