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Altera_Forum's avatar
Altera_Forum
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20 years ago

256MByte boundary not supported ?

Has anyone created a nios2 system with more than 256MByte instruction address range ?

If for example a sdram controller for 256MByte is part of the instruction master of a nios2 cpu then the sopc won't generate the system.

even if you have 128MByte CFI and 128MByte SDRAM you won't be able to add any other sopc module to generate a sopc system.

i thought that this is bug in the past but with Q60SP1 N60 this is also the fact.

if this is correct and there is no workaroung then it would be impossible to create a nios2 system that has an instruction address range of 256MByte or more.

Well Nios2 for embedded application, but you never know ...

can uClinux handle more than 256MByte SDRAM ?

Regards

Michael Schmitt

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    The reason for this limitation is due to the width of the immediate address that can be stored in an instruction word. The largest immediate value is 26 bits wide so that gets you 64MegaWords (32 bit instructions) of address span which equates to 256MB. This only affects the instruction master so if you just need a lot of data storage and can put code elsewhere then you will not hit the 256MB barrier.

    Note this is an address span and not simply a memory size thing. For example if you put two 16MB SDRAMs used to store code in your system and space them apart by a 256MB address span you'll run into this as well.
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Thanks for that explanaition. i thought that it had to do with some addressing limitations but i must have overseen this when reading the altera online documents this morning again.

    as this is a limitation by the opcodes i guess that this will be forever.

    i thought of using uclinux and spent a lot of sdram but i cannot garantee that the memory will only be used for data.

    and as i have to attach an epcs controler as well as the jtag stuff the instruction space for the system is less than 256mbyte. as i can not tell the sdram controller to implement 3 chip selects of 64mb (to have 192mb) i can only choose betwen 128 and 256mbyte but that is not implementable with epcs

    so the design is limited to 128mbyte sdram (for instruction and data) with one sdram controller

    that is a lot of memory but i thought of what would be possible in the future. 640k was enough for DOS and 640MByte is not much nowadays for quartus :-)

    again thanks for your comments.

    regards

    michael schmitt