10.1 breaks NIOS II floating point hardware custom instruction when using VHDL

When I compiled my existing VHDL-based system (which compiled fine in 10.0sp1 and which has a NIOS2 CPU with floating point custom instructions added) with Quartus 10.1, I got the following error:

Error (10258): Verilog HDL error at fpoint_wrapper.v(27): unsupported type for verilog parameter useDivider

The fpoint_wrapper.v (in \altera\10.1\ip\altera\nios2_ip\altera_nios_custom_instr_floating_point_qsys) defines useDivider as:

parameter useDivider = 0;

In fpoint_cpu_0.vhd (which is generated by SOPC) the component is declated as:

component fpoint_wrapper is

generic (

useDivider : boolean := false

);

Help (F1) for error 10258 shows a case exactly like this, where a boolean type is incorrectly given to a verilog module as a parameter. And the recommended action is "Do not pass unsupported value types to Verilog."

The problem is probably coming from fpoint_qsys_hw.tcl, which declares the useDivider parameter's type as BOOLEAN, so SOPC will generate the correct VHDL code for fpoint_wrapper. But Quartus does not seem to be able to pass that boolean parameter to Verilog module ...

Altera recommended to switch to Verilog or wait for a patch!

Since switching to Verilog is obviously not an option to me, I tried making my own fix ...

I changed the following two lines in fpoint_qsys_hw.tcl (in \altera\10.1\ip\altera\nios2_ip\altera_nios_custom_instr_floating_point_qsys)

add_parameter useDivider BOOLEAN false ""

...

set_parameter_property useDivider TYPE BOOLEAN

to

add_parameter useDivider INTEGER 0 ""

...

set_parameter_property useDivider TYPE INTEGER

Now the system compiles.

So if you use floating point hardware custom instruction in your NIOS II CPU and you use VHDL as you system language, you might need to try my fix ...

Waiting for 10.1sp1 ... :mad:

Jari