Forum Discussion
Altera_Forum
Honored Contributor
20 years agoHi MIR,
I've read your old topic but I'm not sure it's my case. My SDRAM signals are not shared on avalon tri-state bus, with other peripheral: I have the SDRAM controller component, whose signals are connected only with my SDRAM. In particular my design has two CPUs, and each one can access SDRAM. Any ideas?