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Dde_B's avatar
Dde_B
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7 years ago

Why won't PLL Reconfig IP allow access to cascaded tap?

So, I have created a PLL with a 50MHz clk in. From there I generate two clocks. C0 = 100MHz, and C1 is 100KHz. The PLL achieves these values by having an M = 12, N=1 and a C0 counter of 6 for t...
Dde_B's avatar
Dde_B
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7 years ago

Hi Gentlemen,

I am using the MAX10 10M08SA I use the ALTTPLL IP in quartus prime (18.xx), I set up clkin at 50MHz, and then C0 I set to 100MHz. I then set up C1 and C2 to be 0.1MHz and it works fine. I actually do something a bit naughty after this and phase shift C1, then XOR the together to get very narrow pulses at twice the freq, but that is an aside. I have proven that I can do this physically using an eval board, but I havent proved physically that I can also do this once I use the reconfig IP. The physical test was done with the ALTPLL config fixed and no reconfig options enabled.

ddB