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Dde_B's avatar
Dde_B
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7 years ago

Why won't PLL Reconfig IP allow access to cascaded tap?

So, I have created a PLL with a 50MHz clk in. From there I generate two clocks. C0 = 100MHz, and C1 is 100KHz. The PLL achieves these values by having an M = 12, N=1 and a C0 counter of 6 for t...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
Hello David, Can you let me know which device you are using ? As Alex mentioned already, I also wonder how tool let you allow to change to 100KHz . I just tried with Arria 10 device. Tool is not letting me allow less than 1MHZ. can you please clarify ? Thank you , Regards, Sree
  • Dde_B's avatar
    Dde_B
    Icon for New Contributor rankNew Contributor
    7 years ago

    Here is the config wizard stating that 0.1MHz is achievable: I have synthesized and implemeted this on the HW.