Forum Discussion
CStub
New Contributor
New ContributorWhy is my altiobuf configured as differential input missing an output?
I am using Cyclone V with Quartus 18.1. I have 2 data input groups, each with a clock and 8 data signals, all differential. Here is a sample of the verilog for clock1 and one data bit. diff_in t...
YuanLi_S_Intel
Regular Contributor
Regular ContributorPerhaps, the design doesn't required that much of LVDS output? or it is not declared in Quartus with that much of bus width.
Sometimes Quartus will optimize that by removing the floating pin.
Anyway, i am glad that your design is working fine now.
