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CStub's avatar
CStub
Icon for New Contributor rankNew Contributor
6 years ago

Why is my altiobuf configured as differential input missing an output?

I am using Cyclone V with Quartus 18.1. I have 2 data input groups, each with a clock and 8 data signals, all differential. Here is a sample of the verilog for clock1 and one data bit. diff_in t...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Perhaps, the design doesn't required that much of LVDS output? or it is not declared in Quartus with that much of bus width.

Sometimes Quartus will optimize that by removing the floating pin.

Anyway, i am glad that your design is working fine now.