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CStub's avatar
CStub
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6 years ago

Why is my altiobuf configured as differential input missing an output?

I am using Cyclone V with Quartus 18.1. I have 2 data input groups, each with a clock and 8 data signals, all differential. Here is a sample of the verilog for clock1 and one data bit. diff_in t...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Craig,

Meaning to say the problem is due to the regenerating of the bitstream?

Thank You

  • CStub's avatar
    CStub
    Icon for New Contributor rankNew Contributor
    6 years ago
    Hi Bruce, This happens after synthesis. I discovered that my design was being optimized away. I fixed by adding *noprune* to the registers that were receiving the data bits, and that prevented the removal. Still don't understand why all of a sudden, and why legitimate logic was deleted. Thanks, Craig