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CStub
New Contributor
New ContributorWhy is my altiobuf configured as differential input missing an output?
I am using Cyclone V with Quartus 18.1. I have 2 data input groups, each with a clock and 8 data signals, all differential. Here is a sample of the verilog for clock1 and one data bit. diff_in t...
CStubNew Contributor
New ContributorFound the answer. It seems that more than half my design was optimized away. I solved it by inserting (*noprune*) before the destination register definition of each input signal. I'm sure it was easier to route, however...
