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Hello,
I have a long standing methodological question about the IP generation tools from Altera. They seem to all generate 2 sets of VHDL/Verilog code: one for synthesis, one for simulation.
But, isn't it asking for trouble ? why can't we just maximize the amount of common code that gets synthetized AND simulated ?
if you have any light on the matter, please share :-)
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Which IPs? Tools output one set of design files. The simulation files are given for testbenching(top level and other associated data files) or occasionally the tool may output simulation model e.g. for PLLs. Can you explain your thoughts in more detail.
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