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AFrei11
New Contributor
New ContributorWhy does the Avalon-ST dual-clock FIFO not transmit the data at the output?
I'm quiet new to FPGA programming and I'm trying to implement the Avalon-ST dual-clock FIFO in my application. As you can see in the picture the FIFO accepts Input Data until the FIFO depth of 16 is ...
AFrei11New Contributor
New ContributorThank you very much for your answer
I have not connected the two resets to the same source.
Now the FIFO is working.
Thank you for your help
