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SThom66's avatar
SThom66
Icon for New Contributor rankNew Contributor
6 years ago

Why does the Avalon-MM bridge add 5 bits of address (33 total) when connecting to a DDR3 memory controller that only needs 28 bits?

I have a Platform Designer design with two DDR3 memory controllers. They both require 28-bits address on the Avalon bus. I want them to look like contiguous memory. I want to connect an Avalon-MM Pip...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Sir,

Welcome to Intel Community.

As I can see the data width from DDR3 controllers and bridge is difference.

You can change the data width to be the same, and then address unit changed to "words".

Meaning, change the bridge data width from 32 bits to 256bits. Then, change the address unit to "words".

Thanks

Regards,

Aida