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MJost3
New Contributor
New ContributorWhy do I see incorrect functionality in hardware when using the dcfifo IP in a Cyclone IV E FPGA design?
In my design targeting a Cyclone IV E FPGA I use several dcfifo FIFOs. I observed that the first write/read FIFO transaction (after the FPGA is configured) sometimes fails in hardware. In such an err...
MJost3New Contributor
New ContributorHi,
I followed the guidance described in the kdb link. Unfortunately, the issue is still there.
However, I found workaround that seems to work: When adding the aclr port of the FIFO and resetting the FIFO at start-up the issue could not be observed anymore.
It seems that the aclr port is needed, altough the data sheet does not state that (the aclr port is optional).
