Forum Discussion

MJost3's avatar
MJost3
Icon for New Contributor rankNew Contributor
6 years ago

Why do I see incorrect functionality in hardware when using the dcfifo IP in a Cyclone IV E FPGA design?

In my design targeting a Cyclone IV E FPGA I use several dcfifo FIFOs. I observed that the first write/read FIFO transaction (after the FPGA is configured) sometimes fails in hardware. In such an err...
MJost3's avatar
MJost3
Icon for New Contributor rankNew Contributor
5 years ago

Hi,

I followed the guidance described in the kdb link. Unfortunately, the issue is still there.

However, I found workaround that seems to work: When adding the aclr port of the FIFO and resetting the FIFO at start-up the issue could not be observed anymore.

It seems that the aclr port is needed, altough the data sheet does not state that (the aclr port is optional).