Forum Discussion
MJost3
New Contributor
New ContributorWhy do I see incorrect functionality in hardware when using the dcfifo IP in a Cyclone IV E FPGA design?
In my design targeting a Cyclone IV E FPGA I use several dcfifo FIFOs. I observed that the first write/read FIFO transaction (after the FPGA is configured) sometimes fails in hardware. In such an err...
RichardT_altera
Super Contributor
Super ContributorI found this kdb.
It seems that additional constrain need to be added. As I do not have a design to test out, could you try to add this in manually per kdb written?
Or, could you share your design so I can duplicate the issue?
