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MJost3's avatar
MJost3
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6 years ago

Why do I see incorrect functionality in hardware when using the dcfifo IP in a Cyclone IV E FPGA design?

In my design targeting a Cyclone IV E FPGA I use several dcfifo FIFOs. I observed that the first write/read FIFO transaction (after the FPGA is configured) sometimes fails in hardware. In such an err...
MJost3's avatar
MJost3
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5 years ago

Hi Shyan,

attached you find all .sdc files we used in this project.

Except the "i214_pld.sdc", "altera_avalon_half_rate_bridge_constraints.sdc" and "spi_fram.sdc" all sdc files were automatically generated by Quartus Tool.