Forum Discussion
MJost3
New Contributor
New ContributorWhy do I see incorrect functionality in hardware when using the dcfifo IP in a Cyclone IV E FPGA design?
In my design targeting a Cyclone IV E FPGA I use several dcfifo FIFOs. I observed that the first write/read FIFO transaction (after the FPGA is configured) sometimes fails in hardware. In such an err...
RichardT_altera
Super Contributor
Super Contributor"sometimes fails in hardware" - may I know is there any specific condition that it fail/pass?
Is your project got write timing sdc and close timing?
