Where can I find utilization of FPGA resource for instantiation of NIOS or MCS51 variant? i.e. How much of the FPGA logic do these IP blocks consume?

There is a document that shows resource utilization needed for NIOS that compiled in every device family https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_nios2_perf.pdf, table 3. Due to different logic architecture, resource being used varies from one device to another. You can get the result from Fitter report by compiling a simple Qsys design with NIOS in your targeting device.