What is the best way for a NIOS II to communicate with the DDR3 SDRAM on the Cyclone 10 GX dev kit?

Hi,

I was digging on the embedded IP peripherals user guide for NIOS II and found this:

“All the IP cores described in this user guide are supported by both Intel® Quartus® Prime Pro Edition and Intel® Quartus® Prime Standard Edition except for the following cores which are only supported by Intel® Quartus® Prime Standard Edition.

• SDRAM Controller Core”

So I looked at the difference between Pro and Standard and the difference is that Pro supports Statix 10, Arria 10 and Cyclone GX 10 and standard supports all the other devices. Looks like SRAM controllers for the latest gen aren’t supported yet. I think this gen has the first hard external memory interfaces so I guess it was a major overhaul. I've seen some reference to testbenches using a NIOS and SDRAM, so I guess is internally developing it. Could Intel confirm if they have something in the works?

In the meantime, what I am trying to do is just build a very basic, low performance SDRAM controller that only has a bust transfer of one and then connect that to the NIOS. The SDRAM half is working fine, but getting it to talk to the NIOS is proving challenging.