What does the arbitration look like for multiple masters to a single slave on an Avalon MM bus?

For question 1,3,4, you can refer to

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-platform-designer.pdf page 136 arbitration.

For question 2,

If the master is starting a burst access indicated by the burstcount signal of more than 1, does the master keep access until the burst is done before the next master gets access?

Yes, basically, they should be waitrequest/valid when u assert the burst. you can refer to the link above page 101.