Forum Discussion
SMcCa9
New Contributor
7 years agoWhat are the Avalon-MM addresses used for the JESD204 IP Core in dynamic reconfiguration for modifying the LMFSK and data rate parameters?
Hello, I am working on a project utilizing the JESD204B IP offered by Intel on an Arria V GZ FPGA using Quartus II Standard 14.0. Part of the project requires dynamic reconfiguration of the JESD204B...
Nathan_R_Intel
Contributor
7 years agoSamual,
Please check my replies to your questions below:
1. Does the JESD IP require a specific naming convention (or generate a .MIF file of a specific naming convention)?
Answer:
No specific naming convention is required. A mif file will be generated during Quartus fitter compilation. The mif file will have an extension of .mif. I just checked the JESD IP using Arria V GZ in Quartus II Standard 14.0 and it is able to generate a .mif file. However, please ensure you have instantiate the Transceiver Reconfiguration
Controller from the IP Catalog and connect it to the JESD204B IP core through the
reconfig_to_xcvr and reconfig_from_xcvr interface. Also check that you have enabled the following features in Transceiver Reconfiguration Controller:
"Enable Channel/PLL reconfiguration"
2. Is this exact format required for the JESD .MIF file, or are other formats supported? If the later, where can I find information about the supported formats?
Answer:
Yes, this is the exact format required. Quartus is supposed to generate this file, hence follow my above guideline and you will be able to generate the .mif file.
The information of MIF file format is documented in the user guide (PG 17-38):
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf
Regards,
Nathan