Forum Discussion
PGigl
Occasional Contributor
Occasional ContributorWe are having issue getting data out of the CIC core during simulation.
We have built up a QSYS design with our own core feeding into a CIC core, feeding into a FIR core. In our simulation we can see signals and data going into the core, and see the appropriate handshak...
JAnde37
New Contributor
New ContributorYes! The initial batch corrupted data coming out of reset was enough to hang the CIC. One simple fix and our design is simulating perfectly. Thank you!
