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PGigl's avatar
PGigl
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

We are having issue getting data out of the CIC core during simulation.

We have built up a QSYS design with our own core feeding into a CIC core, feeding into a FIR core. In our simulation we can see signals and data going into the core, and see the appropriate handshak...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi, Regarding your latest note on the generate test bench for the QSYS file, I believe you are referring to m_293_20091_00_top.qsys. I have tested test bench generation using Q17.0Std (due to no Q18.1Std installed in my local PC) and there is no issue with generation. Will further try out with Q18.1Std when I have access to server later. Please let me know if there is any concern. Thank you. Best regards, Chee Pin