Forum Discussion
PGigl
Occasional Contributor
Occasional ContributorWe are having issue getting data out of the CIC core during simulation.
We have built up a QSYS design with our own core feeding into a CIC core, feeding into a FIR core. In our simulation we can see signals and data going into the core, and see the appropriate handshak...
CheepinC_altera
Regular Contributor
Regular ContributorHi,
Sorry for the delay. Thanks for the update and sharing of the screenshot. Just to update you on the progress on my side, I have replicated your observation of no valid output at CIC following you steps and shared ZIP. It seems like it is a complete design and I have tried to look into if can spot any anomaly. For your information, I have not yet been able to spot any specific anomaly yet. Currently, I am trying to mimic your CIC IP configuration and generate an example design to cross check if example design with your configuration is able to output data.
I will have further discussion with peers specific on your finding where changing the frequency seems to enable output at CH7. Will keep you posted on the progress.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
