Occasional Contributor
Regular Contributor
Occasional ContributorRegarding the errors, they are error codes put out by the core, due to SOP and EOP relationship cased by the FORWARD_PRESSURE defined as "TRUE"
We changed the FORWARD_PRESSURE definition to "FALSE" and the example simulation worked better.
Here is the code from the cicii_example_design_test_program.sv that causes the randomness of the SOP and EOP signals.
fork
begin
while(1) begin
read_input_data_files();
if(`FORWARD_PRESSURE=="TRUE")
begin
src_transaction.idles = ($unsigned($random()) % 10);
end else begin
src_transaction.idles = 0;
end
src_transaction.send_data();
if(source_finished == 0) begin
@(`SRC.signal_min_transaction_queue_size);
end
end
end // source_data_thread
After comparing the two simulations, we noticed differences in the clock rates (ratio between clock frequency and sample rate). After playing with the clock frequency we are now starting to get data out, but only on one channel's time slot.
Can you provide any guidance and/or documentation on setting the clock and sample rates.
Occasional ContributorAttached is the project with original clocking. Under the simulation directory under C:\Intel_projects\micromeritics\CIC_design\m_293_20091_00_top there is a file mentor.do that will run the simulation. You will need to modify the directory locations in the scripts to match your location, else unzip to something like C:\Intel_projects\micromeritics\CIC_design
