Forum Discussion
PGigl
Occasional Contributor
Occasional ContributorWe are having issue getting data out of the CIC core during simulation.
We have built up a QSYS design with our own core feeding into a CIC core, feeding into a FIR core. In our simulation we can see signals and data going into the core, and see the appropriate handshak...
CheepinC_altera
Regular Contributor
Regular ContributorHi Paul,
I will set this case to close for now. Please feel free to open a new case and referred to this case if you have any new inquiry related to the simulation. thank you.
PGiglDo not close the case! The example design simulates, but the real design does not! We noticed that the example design throughs error codes! We went into the example codes BFM and set the "Forward pressure" variable to False, which disabled the "random" functionality, and caused the SOP and EOF inputs to behave normally, and eliminated the error - IN THE EXAMPLE DESIGN. But we still are not getting data out of the real design, though our SOP and EOF match the example (once random was turned off in the example).
